Semiconductor processing for forming integrated circuits requires a series of processing steps. These processing steps include the deposition and patterning of material layers such as insulating layers, polysilicon layers, and metal layers. The material layers are typically patterned using a photoresist layer that is patterned over the material layer using a photomask or reticle. Typically, the photomask has alignment targets or keys that are aligned to fiduciary marks formed in the previous layer on the substrate. However, as the size of integrated circuit features continues to decrease, it becomes increasingly difficult to measure the overlay accuracy of one masking level with respect to the previous level. This overlay metrology problem becomes particularly difficult at submicrometer feature sizes where overlay alignment tolerances are reduced to provide reliable semiconductor devices. One type of overlay measurement is known as diffraction based overlay metrology.